TI 的 16 通道 LVDS 发送器IC SN75LVDS387DGGR/SN65LVDS387DGGR
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High-Speed Differential Line Drivers
This family of four, eight, and sixteen differential line drivers implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the sixteen current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100- load when enabled.
The intended application of this device and signaling technique is for point-to-point and multidrop baseband data transmission over controlled impedance media of approximately 100 . The transmission media can be printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. When used with the companion 16- or 8-channel receivers, the SN65LVDS386 or SN65LVDS388, over 300 million data transfers per second in single-edge clocked systems are possible with very little power. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)
When disabled, the driver outputs are high impedance. Each driver input (A) and enable (EN) have an internal pulldown that will drive the input to a low level when open circuited.
The SN65LVDS387, SN65LVDS389, and SN65LVDS391 are characterized for operation from \x9640°C to 85°C. The SN75LVDS387, SN75LVDS389, and SN75LVDS391 are characterized for operation from 0°C to 70°C.
Four ( 391), Eight ( 389) or Sixteen ( 387) Line Drivers Meet or Exceed the Requirements of ANSI EIA/ TIA-644 Standard
Designed for Signaling Rates up to 630 Mbps With Very Low Radiation (EMI)
Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100- Load
Propagation Delay Times Less Than 2.9 ns
Output Skew Is Less Than 150 ps
Part-to-Part Skew Is Less Than 1.5 ns
35-mW Total Power Dissipation in Each Driver Operating at 200 MHz
Driver Is High Impedance When Disabled or With VCC < 1.5 V
SN65 Version Bus-Pin ESD Protection Exceeds 15 kV
Packaged in Thin Shrink Small-Outline Package With 20-mil Terminal Pitch
Low-Voltage TTL (LVTTL) Logic Inputs Are 5-V Tolerant
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